#ifndef REG_SYSC_CPU_H_
#define REG_SYSC_CPU_H_

#include <stdint.h>
#include "reg_base_addr.h"

#ifdef __cplusplus
extern "C" {
#endif

#define SYSC_CPU ((reg_sysc_cpu_t *)SYSC_CPU_BASE_ADDR)

typedef struct
{
    volatile uint32_t CPU_SYSC; //0x0
    volatile uint32_t GATE_SYS; //0x4
    volatile uint32_t RESERVED0[2];
    volatile uint32_t PD_CPU_CLKG; //0x10
    volatile uint32_t PD_CPU_SRST; //0x14
}reg_sysc_cpu_t;

enum SYSC_CPU_REG_CPU_SYSC_FIELD
{
    SYSC_CPU_CACHE_MEMTST_MASK = (int)0x10,
    SYSC_CPU_CACHE_MEMTST_POS = 4,
    SYSC_CPU_WDT_DBG_MASK = (int)0x100,
    SYSC_CPU_WDT_DBG_POS = 8,
    SYSC_CPU_WWDT_DBG_MASK = (int)0x1000,
    SYSC_CPU_WWDT_DBG_POS = 12,
};

enum SYSC_CPU_REG_GATE_SYS_FIELD
{
    SYSC_CPU_GATE_SYS_EN_MASK = (int)0x1,
    SYSC_CPU_GATE_SYS_EN_POS = 0,
    SYSC_CPU_USB_RX_DIFF_SEL_MASK = (int)0x10,
    SYSC_CPU_USB_RX_DIFF_SEL_POS = 4,
};

enum SYSC_CPU_REG_PD_CPU_CLKG_FIELD
{
    SYSC_CPU_CLKG_SET_CPU_DBG_MASK = (int)0x1,
    SYSC_CPU_CLKG_SET_CPU_DBG_POS = 0,
    SYSC_CPU_CLKG_CLR_CPU_DBG_MASK = (int)0x2,
    SYSC_CPU_CLKG_CLR_CPU_DBG_POS = 1,
    SYSC_CPU_CLKG_SET_CACHE_MASK = (int)0x4,
    SYSC_CPU_CLKG_SET_CACHE_POS = 2,
    SYSC_CPU_CLKG_CLR_CACHE_MASK = (int)0x8,
    SYSC_CPU_CLKG_CLR_CACHE_POS = 3,
    SYSC_CPU_CLKG_SET_QSPI_MASK = (int)0x10,
    SYSC_CPU_CLKG_SET_QSPI_POS = 4,
    SYSC_CPU_CLKG_CLR_QSPI_MASK = (int)0x20,
    SYSC_CPU_CLKG_CLR_QSPI_POS = 5,
    SYSC_CPU_CLKG_SET_USB_MASK = (int)0x40,
    SYSC_CPU_CLKG_SET_USB_POS = 6,
    SYSC_CPU_CLKG_CLR_USB_MASK = (int)0x80,
    SYSC_CPU_CLKG_CLR_USB_POS = 7,
    SYSC_CPU_CLKG_SET_DMAC1_MASK = (int)0x100,
    SYSC_CPU_CLKG_SET_DMAC1_POS = 8,
    SYSC_CPU_CLKG_CLR_DMAC1_MASK = (int)0x200,
    SYSC_CPU_CLKG_CLR_DMAC1_POS = 9,
    SYSC_CPU_CLKG_SET_DMAC2_MASK = (int)0x400,
    SYSC_CPU_CLKG_SET_DMAC2_POS = 10,
    SYSC_CPU_CLKG_CLR_DMAC2_MASK = (int)0x800,
    SYSC_CPU_CLKG_CLR_DMAC2_POS = 11,
    SYSC_CPU_CLKG_SET_ESPI_MASK = (int)0x1000,
    SYSC_CPU_CLKG_SET_ESPI_POS = 12,
    SYSC_CPU_CLKG_CLR_ESPI_MASK = (int)0x2000,
    SYSC_CPU_CLKG_CLR_ESPI_POS = 13,
    SYSC_CPU_CLKG_SET_LPC_MASK = (int)0x4000,
    SYSC_CPU_CLKG_SET_LPC_POS = 14,
    SYSC_CPU_CLKG_CLR_LPC_MASK = (int)0x8000,
    SYSC_CPU_CLKG_CLR_LPC_POS = 15,
    SYSC_CPU_CLKG_SET_CALC_CRC_MASK = (int)0x10000,
    SYSC_CPU_CLKG_SET_CALC_CRC_POS = 16,
    SYSC_CPU_CLKG_CLR_CALC_CRC_MASK = (int)0x20000,
    SYSC_CPU_CLKG_CLR_CALC_CRC_POS = 17,
    SYSC_CPU_CLKG_SET_CALC_MASK = (int)0x40000,
    SYSC_CPU_CLKG_SET_CALC_POS = 18,
    SYSC_CPU_CLKG_CLR_CALC_MASK = (int)0x80000,
    SYSC_CPU_CLKG_CLR_CALC_POS = 19,
    SYSC_CPU_CLKG_SET_BXCAN_MASK = (int)0x100000,
    SYSC_CPU_CLKG_SET_BXCAN_POS = 20,
    SYSC_CPU_CLKG_CLR_BXCAN_MASK = (int)0x200000,
    SYSC_CPU_CLKG_CLR_BXCAN_POS = 21,
    SYSC_CPU_CLKG_SET_CRYPT_MASK = (int)0x400000,
    SYSC_CPU_CLKG_SET_CRYPT_POS = 22,
    SYSC_CPU_CLKG_CLR_CRYPT_MASK = (int)0x800000,
    SYSC_CPU_CLKG_CLR_CRYPT_POS = 23,
    SYSC_CPU_CLKG_SET_ECC_MASK = (int)0x1000000,
    SYSC_CPU_CLKG_SET_ECC_POS = 24,
    SYSC_CPU_CLKG_CLR_ECC_MASK = (int)0x2000000,
    SYSC_CPU_CLKG_CLR_ECC_POS = 25,
    SYSC_CPU_CLKG_SET_CALC_SHA_MASK = (int)0x4000000,
    SYSC_CPU_CLKG_SET_CALC_SHA_POS = 26,
    SYSC_CPU_CLKG_CLR_CALC_SHA_MASK = (int)0x8000000,
    SYSC_CPU_CLKG_CLR_CALC_SHA_POS = 27,
    SYSC_CPU_CLKG_SET_CALC_SM4_MASK = (int)0x10000000,
    SYSC_CPU_CLKG_SET_CALC_SM4_POS = 28,
    SYSC_CPU_CLKG_CLR_CALC_SM4_MASK = (int)0x20000000,
    SYSC_CPU_CLKG_CLR_CALC_SM4_POS = 29,
};

enum SYSC_CPU_REG_PD_CPU_SRST_FIELD
{
    SYSC_CPU_SRST_SET_CACHE_N_MASK = (int)0x4,
    SYSC_CPU_SRST_SET_CACHE_N_POS = 2,
    SYSC_CPU_SRST_CLR_CACHE_N_MASK = (int)0x8,
    SYSC_CPU_SRST_CLR_CACHE_N_POS = 3,
    SYSC_CPU_SRST_SET_QSPI_N_MASK = (int)0x10,
    SYSC_CPU_SRST_SET_QSPI_N_POS = 4,
    SYSC_CPU_SRST_CLR_QSPI_N_MASK = (int)0x20,
    SYSC_CPU_SRST_CLR_QSPI_N_POS = 5,
    SYSC_CPU_SRST_SET_USB_N_MASK = (int)0x40,
    SYSC_CPU_SRST_SET_USB_N_POS = 6,
    SYSC_CPU_SRST_CLR_USB_N_MASK = (int)0x80,
    SYSC_CPU_SRST_CLR_USB_N_POS = 7,
    SYSC_CPU_SRST_SET_DMAC1_MASK = (int)0x100,
    SYSC_CPU_SRST_SET_DMAC1_POS = 8,
    SYSC_CPU_SRST_CLR_DMAC1_MASK = (int)0x200,
    SYSC_CPU_SRST_CLR_DMAC1_POS = 9,
    SYSC_CPU_SRST_SET_DMAC2_MASK = (int)0x400,
    SYSC_CPU_SRST_SET_DMAC2_POS = 10,
    SYSC_CPU_SRST_CLR_DMAC2_MASK = (int)0x800,
    SYSC_CPU_SRST_CLR_DMAC2_POS = 11,
    SYSC_CPU_SRST_SET_ESPI_MASK = (int)0x1000,
    SYSC_CPU_SRST_SET_ESPI_POS = 12,
    SYSC_CPU_SRST_CLR_ESPI_MASK = (int)0x2000,
    SYSC_CPU_SRST_CLR_ESPI_POS = 13,
    SYSC_CPU_SRST_SET_LPC_MASK = (int)0x4000,
    SYSC_CPU_SRST_SET_LPC_POS = 14,
    SYSC_CPU_SRST_CLR_LPC_MASK = (int)0x8000,
    SYSC_CPU_SRST_CLR_LPC_POS = 15,
    SYSC_CPU_SRST_SET_CALC_CRC_MASK = (int)0x10000,
    SYSC_CPU_SRST_SET_CALC_CRC_POS = 16,
    SYSC_CPU_SRST_CLR_CALC_CRC_MASK = (int)0x20000,
    SYSC_CPU_SRST_CLR_CALC_CRC_POS = 17,
    SYSC_CPU_SRST_SET_CALC_MASK = (int)0x40000,
    SYSC_CPU_SRST_SET_CALC_POS = 18,
    SYSC_CPU_SRST_CLR_CALC_MASK = (int)0x80000,
    SYSC_CPU_SRST_CLR_CALC_POS = 19,
    SYSC_CPU_SRST_SET_BXCAN_MASK = (int)0x100000,
    SYSC_CPU_SRST_SET_BXCAN_POS = 20,
    SYSC_CPU_SRST_CLR_BXCAN_MASK = (int)0x200000,
    SYSC_CPU_SRST_CLR_BXCAN_POS = 21,
    SYSC_CPU_SRST_SET_CRYPT_MASK = (int)0x400000,
    SYSC_CPU_SRST_SET_CRYPT_POS = 22,
    SYSC_CPU_SRST_CLR_CRYPT_MASK = (int)0x800000,
    SYSC_CPU_SRST_CLR_CRYPT_POS = 23,
    SYSC_CPU_SRST_SET_ECC_MASK = (int)0x1000000,
    SYSC_CPU_SRST_SET_ECC_POS = 24,
    SYSC_CPU_SRST_CLR_ECC_MASK = (int)0x2000000,
    SYSC_CPU_SRST_CLR_ECC_POS = 25,
    SYSC_CPU_SRST_SET_CALC_SHA_MASK = (int)0x4000000,
    SYSC_CPU_SRST_SET_CALC_SHA_POS = 26,
    SYSC_CPU_SRST_CLR_CALC_SHA_MASK = (int)0x8000000,
    SYSC_CPU_SRST_CLR_CALC_SHA_POS = 27,
    SYSC_CPU_SRST_SET_CALC_SM4_MASK = (int)0x10000000,
    SYSC_CPU_SRST_SET_CALC_SM4_POS = 28,
    SYSC_CPU_SRST_CLR_CALC_SM4_MASK = (int)0x20000000,
    SYSC_CPU_SRST_CLR_CALC_SM4_POS = 29,
};

#ifdef __cplusplus
}
#endif

#endif